Bigger designs with hundred of cores are creating an explosion in the volume of scan test data, significantly bumping up the amount of time spent on test. That raises the cost of test, forcing ...

Memristors in action: Sort-in-memory, a nervous system for robots, RF signal processing. Researchers from Peking University ...

This report focuses on different interconnect structures, such as lines, vias, buses, and networks-on-chip, and how they’re ...

A new technical paper titled “Augmenting Von Neumann’s Architecture for an Intelligent Future” was published by researchers ...

EMLC and 30 years of leadership by Dr. Behringer – all a good reason for a brief review. EMLC was first held in Munich in ...

Flip chip lidded ball grid array (FCLBGA) packaging technology, which is commonly used in high-performance computing ...

In the world of EDA, Jay Vleeschhouwer, managing director of software research at Griffin Securities, needs no introduction.

Rationale and guidance for acquiring and maintaining SEMI E187-0122 tool equipment cybersecurity compliance. Cyber threats ...

Certain non-killer but marginal wafer defects can escape detection if they have sufficient electrical connectivity.

AI and HPC are fueling much-needed investment in panel-level tooling and processes. An insatiable demand for logic to memory ...

What is CMOS 2.0? At its core, CMOS 2.0 is an effort to move beyond the limitations of a single monolithic die. Rather than ...

Despite the AI hype, ML tools really are proving valuable for leading-edge chip manufacturing. More aggressive feature ...